As semiconductor devices have become more highly integrated, an interval between conductive patterns has become smaller, and crosstalk between the conductive patterns may occur. Also, a parasitic capacitance between adjacent conductive patterns intended to be electrically isolated from one another by an insulating layer, may increase. For example, when the conductive patterns are bit lines of a memory device, the parasitic capacitance between the bit lines may interrupt the flow of an electric signal transmitted to a circuit, and reduce the bit line sensing margin. Accordingly, a technique of forming spacer structures (having a lower dielectric constant than the conductive patterns) between the conductive patterns has been used to reduce the parasitic capacitance between the conductive patterns.